Static charge decay analysis of MOS circuits

Posted at 10:00 am on 12/05/1991 by Dr. Rahul Razdan

It is shown how symbolic analysis provides a practical solution to the charge decay verification problem and overcomes the uncertainty of pattern dependent verifications. The symbolic approach was successfully used to verify large CMOS VLSI designs for charge decay.

Full Article in Proceedings of the IEEE 1991, Custom Integrated Circuits Conference, 1991.

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