Load/ store execution order violations in an out-of-order processor are reduced by determining whether a source address of a load instruction is the same as a destination address of a store instruction on which execution the load instruction depends. If they are the same, then execution of the load instruction is delayed until execution of the store instruction. In an system where virtual registers are mapped to a physical register, the physical registers mapped by the store and load instructions are compared. A table has entries corresponding to instructions in an instruction queue. In each table entry corresponding to a store instruction, the store instruction's destination address offset and physical register reference are saved. A load instruction's source address offset and physical reference are compared with each of the table entries corresponding to store instructions to determine whether a dependency exists. Furthermore, a matrix also has row entries corresponding to instruction queue entries. In addition, each matrix row has a separate indicator for each instruction queue entry. Upon determining that a load instruction is dependent upon a store instruction, the indicator corresponding to the store instruction in the matrix row corresponding to the load instruction is marked, while an indicator is “unmarked” when the corresponding store instruction issues. Execution of any load instruction is delayed while any indicator in the load instruction's corresponding matrix row is marked. When a store instruction executes, all indicators in the column corresponding to the store instruction are unmarked (Full Patent Here).