Parametric process variations, which are inherent in the manufacture of complex digital circuits, can cause variations in the timing characteristics of a digital device. These device timing variations can cause catastrophic failures to the intended logical operation of the whole design. Min-Max Timing Simulation is a simulation technique which is well suited to verify that a given design functions correctly, even under the influence of parametric process variations. Unfortunately, in the past, Min-Max Timing Simulation has been very expensive in simulation CPU time and in the amount of memory consumed. We present a technique, Concurrent Min-Max Simulation (CMMS), which employs the techniques developed in Concurrent Fault Simulation, to elegantly solve the Min-Max Timing simulation problem.